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Formal Methods

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Computation Tree Logic (CTL)

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A branching-time logic, distinct from LTL, that can specify branching structures like computation trees. Applied in defining and checking properties of reactive systems.

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Turing Machine

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A theoretical construct that represents a computing machine. Used to understand the limits of what can be computed and serves as a standard for computability.

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Algebraic Specification

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A method to formally specify abstract data types in a sheer algebraic way. Employed in the stepwise refinement and implementation of software systems.

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Formal Verification

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The act of proving or disproving the correctness of intended algorithms underlying a system with respect to a certain formal specification or property, using formal methods of mathematics.

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Linear Temporal Logic (LTL)

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A modal temporal logic with modalities referring to time, where formulas always interpret paths (or runs) through a model. Used to specify and reason about the temporal aspects within model checking.

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Buchi Automata

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A type of finite automaton modeled for infinite inputs. Used to model and check properties of systems that run indefinitely like operating systems.

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Process Calculus

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A family of approaches for formally modeling concurrent systems. Used as a tool for specifying and verification of high-level descriptions of communications between systems.

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Binary Decision Diagram (BDD)

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A data structure that is used to represent and manipulate Boolean functions efficiently. Used in design and verification of hardware and software, primarily in reducing complexity.

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Hoare Logic

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A formal system with a set of logical rules for reasoning rigorously about the correctness of computer programs. Used to prove the correctness of algorithms.

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Abstract Interpretation

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A theory that provides a framework for constructing abstract models of computer programs and reasoning about their properties. Used mainly for static program analysis.

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Model Checking

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An automated technique for verifying finite state concurrent systems. Utilized in hardware and software design to find design errors in systems.

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Temporal Logic

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A modal logic with modalities referencing time. Used in specifying and reasoning about the temporal properties of systems within formal verification.

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