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Computer Architecture Basics
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CU
Control Unit, part of the CPU that directs the operation of the processor.
Pipeline
A set of data processing elements connected in series, where the output of one element is the input of the next.
Superscalar Processor
A type of microprocessor architecture that can execute more than one instruction during a single clock cycle.
Speculative Execution
A computer system's ability to predict which instructions might be executed in the future and execute them ahead of time.
MMX
Multimedia Extensions, a SIMD instruction set designed by Intel, introduced to enhance the performance of multimedia and communication operations.
Floating Point Unit (FPU)
A part of the computer's CPU or a separate coprocessor that performs arithmetic operations on floating-point numbers.
ROM
Read-Only Memory, non-volatile memory used to store firmware and important boot data.
Registers
Small, fast storage locations within the CPU used to hold temporary data and instructions.
Out-of-order Execution
A method used in most high-performance microprocessors to make use of otherwise wasted instruction cycles by rearranging the order of instructions to avoid idle processor cycles.
Microarchitecture
The way a given instruction set architecture (ISA) is implemented on a processor, in a particular manufacturing process.
Instruction Set
The set of all operations that can be executed by a processor.
Clock Speed
The speed at which a processor executes instructions, measured in hertz.
Interrupt Service Routine (ISR)
A special block of code associated with a specific interrupt condition, which is executed when the interrupt occurs.
Level-3 Cache (L3 Cache)
Even larger cache memory available on some processors to serve as a third stage of caching, often shared between all CPU cores.
Non-Uniform Memory Access (NUMA)
A computer memory design used in multiprocessing, where the memory access time depends on the memory location relative to the processor.
Cache Coherence
A protocol for managing the caches of a multiprocessor system so that no data becomes out of sync.
Virtual Machine
An emulation of a computer system that enables an operating system to run as if it were on physical hardware.
Interrupt
A signal to the processor emitted by hardware or software indicating an event that needs immediate attention.
Embedded System
A combination of computer hardware and software designed for a specific function or functions within a larger system.
Level-2 Cache (L2 Cache)
A larger cache memory than L1, it may be on the CPU or separate, and it serves as a secondary stage of caching.
RAM
Random Access Memory, a form of computer memory that can be read and changed in any order.
Address Space
The total number of memory addresses that a processor can use to access memory.
Instruction Pipeline
A technique used in the design of CPUs to increase their instruction throughput (the number of instructions that can be executed in a unit of time).
Supervisor Mode
A mode of operation in a computer that has full access to all hardware and can execute any instruction.
Multithreading
A technique by which a single set of code can be run by multiple processors at different stages of execution.
Virtual Memory
A memory management technique that provides an 'idealized abstraction of the storage resources' that are actually available on a given machine.
Branch Predictor
A digital circuit in a CPU that tries to guess which way a branch (e.g., an 'if' or a 'while' statement) will go before this is known for sure.
Von Neumann Architecture
A computing architecture where program instructions and data share the same memory space.
Multiprocessing
The use of two or more CPUs (processing units) within a single computer system.
Bus
Electrical pathways used for communication between different components of a computer.
CISC
Complex Instruction Set Computer; a CPU design strategy with a large set of instructions, some of which may execute complex tasks.
Concurrency
The ability of a computer system to perform multiple tasks or processes simultaneously.
SSE
Streaming SIMD Extensions, a multimedia instruction set more advanced than MMX designed to allow single instruction operations on multiple data.
User Mode
A mode in computer operation that restricts application software from having direct access to hardware resources.
Fetch-Execute Cycle
The basic operation cycle of a computer, which involves retrieving an instruction (fetch) from memory and executing it.
Harvard Architecture
A computer architecture with physically separate storage and signal pathways for instructions and data.
Instruction Level Parallelism
A measure of how many of the operations in a computer program can be performed simultaneously.
Quantum Computing
An area of computing focused on developing computer technology based on the principles of quantum theory, which explains the nature of energy and matter on the quantum (atomic and subatomic) level.
ALU
Arithmetic Logic Unit, part of the CPU that handles arithmetic and logical operations.
Cache Memory
A small, fast type of volatile computer memory that provides high-speed data access to the CPU.
Memory Hierarchy
Organization of storage types in a computer system based on speed and size.
Word Size
Refers to the number of bits processed by the CPU's ALU in a single operation.
Direct Memory Access (DMA)
A feature that allows certain hardware subsystems within a computer to access system memory independently of the central processing unit (CPU).
MIPS
Million Instructions Per Second, a measure of a computer's processor speed.
Level-1 Cache (L1 Cache)
The smallest and fastest type of cache memory, located on the CPU, designed to supply the processor with the most frequently requested data and instructions.
Memory Management Unit (MMU)
A computer hardware unit that handles all memory and caching operations associated with the processor.
CPU
Central Processing Unit, the primary component of a computer that processes instructions.
RISC
Reduced Instruction Set Computer; a CPU design strategy based on simple instructions and efficient use of pipelining.
Associative Cache
A type of cache memory where the contents can be rapidly located by the content itself, rather than by a specific address or location.
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