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Computer Architecture Basics

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CU

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Control Unit, part of the CPU that directs the operation of the processor.

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Pipeline

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A set of data processing elements connected in series, where the output of one element is the input of the next.

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Superscalar Processor

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A type of microprocessor architecture that can execute more than one instruction during a single clock cycle.

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Speculative Execution

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A computer system's ability to predict which instructions might be executed in the future and execute them ahead of time.

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MMX

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Multimedia Extensions, a SIMD instruction set designed by Intel, introduced to enhance the performance of multimedia and communication operations.

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Floating Point Unit (FPU)

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A part of the computer's CPU or a separate coprocessor that performs arithmetic operations on floating-point numbers.

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ROM

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Read-Only Memory, non-volatile memory used to store firmware and important boot data.

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Registers

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Small, fast storage locations within the CPU used to hold temporary data and instructions.

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Out-of-order Execution

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A method used in most high-performance microprocessors to make use of otherwise wasted instruction cycles by rearranging the order of instructions to avoid idle processor cycles.

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Microarchitecture

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The way a given instruction set architecture (ISA) is implemented on a processor, in a particular manufacturing process.

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Instruction Set

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The set of all operations that can be executed by a processor.

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Clock Speed

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The speed at which a processor executes instructions, measured in hertz.

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Interrupt Service Routine (ISR)

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A special block of code associated with a specific interrupt condition, which is executed when the interrupt occurs.

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Level-3 Cache (L3 Cache)

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Even larger cache memory available on some processors to serve as a third stage of caching, often shared between all CPU cores.

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Non-Uniform Memory Access (NUMA)

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A computer memory design used in multiprocessing, where the memory access time depends on the memory location relative to the processor.

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Cache Coherence

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A protocol for managing the caches of a multiprocessor system so that no data becomes out of sync.

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Virtual Machine

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An emulation of a computer system that enables an operating system to run as if it were on physical hardware.

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Interrupt

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A signal to the processor emitted by hardware or software indicating an event that needs immediate attention.

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Embedded System

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A combination of computer hardware and software designed for a specific function or functions within a larger system.

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Level-2 Cache (L2 Cache)

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A larger cache memory than L1, it may be on the CPU or separate, and it serves as a secondary stage of caching.

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RAM

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Random Access Memory, a form of computer memory that can be read and changed in any order.

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Address Space

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The total number of memory addresses that a processor can use to access memory.

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Instruction Pipeline

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A technique used in the design of CPUs to increase their instruction throughput (the number of instructions that can be executed in a unit of time).

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Supervisor Mode

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A mode of operation in a computer that has full access to all hardware and can execute any instruction.

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Multithreading

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A technique by which a single set of code can be run by multiple processors at different stages of execution.

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Virtual Memory

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A memory management technique that provides an 'idealized abstraction of the storage resources' that are actually available on a given machine.

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Branch Predictor

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A digital circuit in a CPU that tries to guess which way a branch (e.g., an 'if' or a 'while' statement) will go before this is known for sure.

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Von Neumann Architecture

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A computing architecture where program instructions and data share the same memory space.

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Multiprocessing

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The use of two or more CPUs (processing units) within a single computer system.

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Bus

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Electrical pathways used for communication between different components of a computer.

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CISC

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Complex Instruction Set Computer; a CPU design strategy with a large set of instructions, some of which may execute complex tasks.

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Concurrency

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The ability of a computer system to perform multiple tasks or processes simultaneously.

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SSE

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Streaming SIMD Extensions, a multimedia instruction set more advanced than MMX designed to allow single instruction operations on multiple data.

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User Mode

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A mode in computer operation that restricts application software from having direct access to hardware resources.

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Fetch-Execute Cycle

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The basic operation cycle of a computer, which involves retrieving an instruction (fetch) from memory and executing it.

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Harvard Architecture

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A computer architecture with physically separate storage and signal pathways for instructions and data.

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Instruction Level Parallelism

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A measure of how many of the operations in a computer program can be performed simultaneously.

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Quantum Computing

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An area of computing focused on developing computer technology based on the principles of quantum theory, which explains the nature of energy and matter on the quantum (atomic and subatomic) level.

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ALU

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Arithmetic Logic Unit, part of the CPU that handles arithmetic and logical operations.

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Cache Memory

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A small, fast type of volatile computer memory that provides high-speed data access to the CPU.

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Memory Hierarchy

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Organization of storage types in a computer system based on speed and size.

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Word Size

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Refers to the number of bits processed by the CPU's ALU in a single operation.

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Direct Memory Access (DMA)

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A feature that allows certain hardware subsystems within a computer to access system memory independently of the central processing unit (CPU).

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MIPS

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Million Instructions Per Second, a measure of a computer's processor speed.

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Level-1 Cache (L1 Cache)

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The smallest and fastest type of cache memory, located on the CPU, designed to supply the processor with the most frequently requested data and instructions.

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Memory Management Unit (MMU)

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A computer hardware unit that handles all memory and caching operations associated with the processor.

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CPU

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Central Processing Unit, the primary component of a computer that processes instructions.

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RISC

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Reduced Instruction Set Computer; a CPU design strategy based on simple instructions and efficient use of pipelining.

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Associative Cache

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A type of cache memory where the contents can be rapidly located by the content itself, rather than by a specific address or location.

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